1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a design method of this semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device including a domino circuit cell array and a design method of this semiconductor integrated circuit device.
2. Related Art
In designing an LSI capable of high-speed operation, in a static circuit composed of usual CMOS circuits, the area occupied by the static circuit has become increasingly insufficient in terms of an integration degree. Particularly, in designing a processor which operates at frequencies exceeding 1 GHz or the like, this situation becomes especially remarkable. For this reason, in such designing, a dynamic circuit is often used in place of a static circuit. A domino circuit is widely known as one of such dynamic circuits and an increasing number of domino circuits have been field proven (refer to the Japanese Patent Laid-Open No. 63-108814 and the Japanese Patent Laid-Open No. 10-336015).
However, almost all designing using a domino circuit has hitherto been manually performed. This is ascribed to design problems peculiar to a domino circuit which are different from those of a static circuit. One of the problems is as follows. That is, after the design of a fundamental cell circuit (which may sometimes be called a primitive block), in the case of a static circuit, it is necessary to verify only a DC noise margin, whereas in the case of a domino circuit, it is necessary to perform multiple verifications of an AC noise margin, precharge time, a charge share, etc. in addition to the verification of a DC noise margin.
As a result of this, in the case of a domino circuit, design items are not prepared as a standard library unlike the case of a static circuit and, it is necessary for the designer to prepare all design items that require verification and to verify them. Compared to a static circuit, a domino circuit is weak in noise and has a high possibility of wrong logic actions. In addition, unlike the case of a static circuit, it is necessary to distribute clocks for dynamic action to all domino circuit cells. After the verification of delays is performed after the completion of layout design, it is necessary to determine clocks to be distributed while checking restrictions for a delay time for each domino circuit stage and for a required clock cycle. Therefore, modifications and amounts of turning back become large when delay restrictions cannot be met.
Design methods of a semiconductor integrated circuit including the above-described domino circuit cell array have problems as described below. The first problem is that because domino circuit designing which has thitherto been performed is based on manual design, the automation of design is difficult. The second problem is that because of the difficulty of the automation of design, the scope of application of a domino circuit is limited to narrow places and applicable places cannot be expanded to a wider range.